Integrated circuit constructions typically comprise a semiconductive material substrate having circuitry formed thereover. The circuitry can fall within different classes of circuit types, with one exemplary class being memory devices, and another exemplary class being logic devices. For instance, memory chips will frequently comprise an array of memory devices, and will further comprise logic devices peripheral to the memory array. Exemplary memory devices are dynamic random access memory (DRAM) devices.
The memory devices and logic devices can have different desired operating parameters relative to one another. For instance, a highly desired aspect of memory devices can be that such devices have very low off current. In other words it can be desired that very little, if any, current trickle through the devices in an off state. In contrast, peripheral devices can frequently tolerate a higher off current than memory devices, but it can be desired that the peripheral devices have enhanced mobility of charge within semiconductive substrates incorporated into the devices.
It can be difficult to incorporate memory devices and logic devices into a single integrated circuit while optimizing performance parameters of both the memory devices and logic devices. It would therefore be desirable to develop new methods of forming semiconductor circuitry which could enable optimization of memory device parameters and logic device parameters when the memory devices and logic devices are incorporated into a common integrated circuit construction.